The subject matter disclosed herein relates to solutions for controlling the bulk bias voltage in an integrated circuit chip. More specifically, the subject matter disclosed herein relates to solutions for controlling the bulk bias voltage in an integrated circuit chip fabricated in an extremely thin silicon-on-insulator (ETSOI) process.
Conventionally, attempts have been made to improve the performance of complementary-metal oxide semiconductor (CMOS) devices (e.g. transistors), and/or decrease the off-state current leakage of these devices. Some prior approaches have included the use of adaptive body biasing to modify the bias voltage across portions of these devices. More particularly, these approaches have used a location-specific circuit to control the voltage applied to individual transistors, or particular groups of transistors using adaptive body biasing. However, these conventional approaches still require design and implementation of specific circuitry and isolating structures, which may be both costly and space-consuming.